Commit 3a80fbe2 authored by bg's avatar bg

forgotten bmw stuff

parent 2a477937
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/* bmw_small-asm.S */
/*
This file is part of the ARM-Crypto-Lib.
Copyright (C) 2006-2010 Daniel Otte (daniel.otte@rub.de)
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* \file bmw_small-asm.S
* \author Daniel Otte
* \email daniel.otte@rub.de
* \date 2010-05-23
* \license GPLv3 or later
*
*/
.syntax unified
.text
.thumb
.align 2
.thumb_func
/*
#define S32_1(x) ( (SHR32((x), 1)) ^ \
(SHL32((x), 2)) ^ \
(ROTL32((x), 8)) ^ \
(ROTR32((x), 9)) )
#define S32_2(x) ( (SHR32((x), 2)) ^ \
(SHL32((x), 1)) ^ \
(ROTL32((x), 12)) ^ \
(ROTR32((x), 7)) )
#define S32_3(x) ( (SHR32((x), 2)) ^ \
(SHL32((x), 2)) ^ \
(ROTL32((x), 15)) ^ \
(ROTR32((x), 3)) )
#define S32_4(x) ( (SHR32((x), 1)) ^ (x))
#define S32_5(x) ( (SHR32((x), 2)) ^ (x))
*/
.global bmw_s32_0
.text
.thumb
.align 2
.thumb_func
.type bmw_s32_0, %function
bmw_s32_0:
mov r1, r0
lsrs r0, r0, #1
eor r0, r0, r1, lsl #3
eor r0, r0, r1, ror #28
eor r0, r0, r1, ror #13
bx lr
.global bmw_s32_1
.text
.thumb
.align 2
.thumb_func
.type bmw_s32_1, %function
bmw_s32_1:
mov r1, r0
lsrs r0, r0, #1
eor r0, r0, r1, lsl #2
eor r0, r0, r1, ror #24
eor r0, r0, r1, ror #9
bx lr
.global bmw_s32_2
.text
.thumb
.align 2
.thumb_func
.type bmw_s32_2, %function
bmw_s32_2:
mov r1, r0
lsrs r0, r0, #2
eor r0, r0, r1, lsl #1
eor r0, r0, r1, ror #20
eor r0, r0, r1, ror #7
bx lr
.global bmw_s32_3
.text
.thumb
.align 2
.thumb_func
.type bmw_s32_3, %function
bmw_s32_3:
mov r1, r0
lsrs r0, r0, #2
eor r0, r0, r1, lsl #2
eor r0, r0, r1, ror #17
eor r0, r0, r1, ror #3
bx lr
.global bmw_s32_4
.text
.thumb
.align 2
.thumb_func
.type bmw_s32_4, %function
bmw_s32_4:
eor r0, r0, r0, lsr #1
bx lr
.global bmw_s32_5
.text
.thumb
.align 2
.thumb_func
.type bmw_s32_5, %function
bmw_s32_5:
eor r0, r0, r0, lsr #2
bx lr
.global bmw_small_f0
.text
.thumb
.align 2
.thumb_func
.type bmw_small_f0, %function
/*
* param q: r0
* param h: r1
* param m: r2
*/
bmw_small_f0:
push {r4-r11, r14}
sub sp, sp, #64
mov r3, sp
adds r3, r3, #4
10:
ldmia r1!, {r4,r6,r8,r10}
ldmia r2!, {r5,r7,r9,r11}
eors r4, r5
eors r6, r7
eors r8, r9
eors r10, r11
stmia r3!, {r4,r6,r8,r10}
ldmia r1!, {r4,r6,r8,r10}
ldmia r2!, {r5,r7,r9,r11}
eors r4, r5
eors r6, r7
eors r8, r9
eors r10, r11
stmia r3!, {r4,r6,r8,r10}
ldmia r1!, {r4,r6,r8,r10}
ldmia r2!, {r5,r7,r9,r11}
eors r4, r5
eors r6, r7
eors r8, r9
eors r10, r11
stmia r3!, {r4,r6,r8,r10}
ldmia r1!, {r4,r6,r8,r10}
ldmia r2!, {r5,r7,r9,r11}
eors r4, r5
eors r6, r7
eors r8, r9
eors r10, r11
stmia r3!, {r4,r6,r8,r10}
/* --- */
subs r1, r1, #64
subs r3, r3, #64
/*
q[ 0] = (+ h[ 5] - h[ 7] + h[10] + h[13] + h[14]);
q[ 3] = (+ h[ 8] - h[10] + h[13] + h[ 0] - h[ 1]);
q[ 6] = (- h[11] + h[13] - h[ 0] - h[ 3] + h[ 4]);
q[ 9] = (+ h[14] + h[ 0] - h[ 3] + h[ 6] - h[ 7]);
q[12] = (+ h[ 1] + h[ 3] - h[ 6] - h[ 9] + h[10]);
q[15] = (- h[ 4] - h[ 6] - h[ 9] + h[12] + h[13]);
q[ 2] = (+ h[ 7] + h[ 9] - h[12] + h[15] + h[ 0]);
q[ 5] = (+ h[10] - h[12] + h[15] - h[ 2] + h[ 3]);
q[ 8] = (+ h[13] - h[15] + h[ 2] - h[ 5] - h[ 6]);
q[11] = (- h[ 0] - h[ 2] - h[ 5] + h[ 8] + h[ 9]);
q[14] = (+ h[ 3] - h[ 5] + h[ 8] - h[11] - h[12]);
q[ 1] = (+ h[ 6] - h[ 8] + h[11] + h[14] - h[15]);
q[ 4] = (+ h[ 9] - h[11] - h[14] + h[ 1] + h[ 2]);
q[ 7] = (- h[12] - h[14] + h[ 1] - h[ 4] - h[ 5]);
q[10] = (+ h[15] - h[ 1] - h[ 4] - h[ 7] + h[ 8]);
q[13] = (+ h[ 2] + h[ 4] + h[ 7] + h[10] + h[11]);
*/
ldr r4, [r3, #(5*4)]
ldr r5, [r3, #(7*4)]
ldr r6, [r3, #(10*4)]
ldr r7, [r3, #(13*4)]
ldr r8, [r3, #(14*4)]
ldr r9, [r3, #(8*4)]
ldr r10, [r3, #(11*4)]
subs r2, r4, r5
adds r2, r2, r6
adds r2, r2, r7
adds r2, r2, r8
str r2, [r0, #0]
ldr r4, [r3, #0]
ldr r5, [r3, #1]
subs r2, r9, r6
adds r2, r2, r7
adds r2, r2, r4
subs r2, r2, r5
add sp, sp, #64
pop {r4-r11, pc}
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/* bmw_small_speed_asm_f0.S */
/*
This file is part of the ARM-Crypto-Lib.
Copyright (C) 2006-2010 Daniel Otte (daniel.otte@rub.de)
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
.syntax unified
.macro S32_0 out:req in:req
lsr \out, \in, #1
eor \out, \out, \in, LSL #3
eor \out, \out, \in, ROR #28
eor \out, \out, \in, ROR #13
.endm
.macro S32_1 out:req in:req
lsr \out, \in, #1
eor \out, \out, \in, LSL #2
eor \out, \out, \in, ROR #24
eor \out, \out, \in, ROR #9
.endm
.macro S32_2 out:req in:req
lsr \out, \in, #2
eor \out, \out, \in, LSL #1
eor \out, \out, \in, ROR #20
eor \out, \out, \in, ROR #7
.endm
.macro S32_3 out:req in:req
lsr \out, \in, #2
eor \out, \out, \in, LSL #2
eor \out, \out, \in, ROR #17
eor \out, \out, \in, ROR #3
.endm
.macro S32_4 in:req
eor \in, \in, \in, LSR #1
.endm
.macro S32_5 in:req
eor \in, \in, \in, LSR #2
.endm
#define T00_ADDR [SP, #(15-3)*4]
#define T01_ADDR [SP, #(15-2)*4]
#define T02_ADDR [SP, #(15-1)*4]
#define T03_ADDR [SP, #(15-0)*4]
#define T04_ADDR [SP, #(15-7)*4]
#define T05_ADDR [SP, #(15-6)*4]
#define T06_ADDR [SP, #(15-5)*4]
#define T07_ADDR [SP, #(15-4)*4]
#define T08_ADDR [SP, #(15-11)*4]
#define T09_ADDR [SP, #(15-10)*4]
#define T10_ADDR [SP, #(15-9)*4]
#define T11_ADDR [SP, #(15-8)*4]
#define T12_ADDR [SP, #(15-15)*4]
#define T13_ADDR [SP, #(15-14)*4]
#define T14_ADDR [SP, #(15-13)*4]
#define T15_ADDR [SP, #(15-12)*4]
.text
.align 2
.thumb
.thumb_func
.type bmw_small_f0, %function
.global bmw_small_f0
bmw_small_f0:
push {r4, r5, r6, r7, r8, r9, r10, r11, r12, r14}
/* memxor(<STACK>, h, m, 16) */
ldmia r1!, {r4, r5, r6, r7}
ldmia r2!, {r8, r9, r10, r11}
eor r4, r8
eor r5, r9
eor r6, r10
eor r7, r11
push {r4, r5, r6, r7}
ldmia r1!, {r4, r5, r6, r7}
ldmia r2!, {r8, r9, r10, r11}
eor r4, r8
eor r5, r9
eor r6, r10
eor r7, r11
push {r4, r5, r6, r7}
ldmia r1!, {r4, r5, r6, r7}
ldmia r2!, {r8, r9, r10, r11}
eor r4, r8
eor r5, r9
eor r6, r10
eor r7, r11
push {r4, r5, r6, r7}
ldmia r1!, {r4, r5, r6, r7}
ldmia r2!, {r8, r9, r10, r11}
eor r4, r8
eor r5, r9
eor r6, r10
eor r7, r11
push {r4, r5, r6, r7}
sub r1, #16*4
#include "f0_small_autogen.i"
add SP, #16*4
pop {r4, r5, r6, r7, r8, r9, r10, r11, r12, PC}
/* bmw_small_speed_asm_f0.S */
/*
This file is part of the ARM-Crypto-Lib.
Copyright (C) 2006-2010 Daniel Otte (daniel.otte@rub.de)
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
.syntax unified
.macro S32_0 out:req in:req
lsr \out, \in, #1
eor \out, \out, \in, LSL #3
eor \out, \out, \in, ROR #28
eor \out, \out, \in, ROR #13
.endm
.macro S32_1 out:req in:req
lsr \out, \in, #1
eor \out, \out, \in, LSL #2
eor \out, \out, \in, ROR #24
eor \out, \out, \in, ROR #9
.endm
.macro S32_2 out:req in:req
lsr \out, \in, #2
eor \out, \out, \in, LSL #1
eor \out, \out, \in, ROR #20
eor \out, \out, \in, ROR #7
.endm
.macro S32_3 out:req in:req
lsr \out, \in, #2
eor \out, \out, \in, LSL #2
eor \out, \out, \in, ROR #17
eor \out, \out, \in, ROR #3
.endm
.macro S32_4 in:req
eor \in, \in, \in, LSR #1
.endm
.macro S32_5 in:req
eor \in, \in, \in, LSR #2
.endm
.text
.align 2
.thumb
.thumb_func
.type bmw_small_f0, %function
.global bmw_small_f0
bmw_small_f0:
push {r4, r5, r6, r7, r8, r9, r10, r11, r12, r14}
#include "f0_small_autogen_mix.i"
pop {r4, r5, r6, r7, r8, r9, r10, r11, r12, PC}
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/*=== W[ 0] ===*/
ldr r14, T05_ADDR
ldr r12, T07_ADDR
ldr r11, T10_ADDR
ldr r10, T13_ADDR
ldr r9, T14_ADDR
sub r3, r9, r12
/*(-- should do +10, +13, +1tr, +5 --)*/
add r5, r11, r10
add r5, r3
add r5, r14
S32_0 r8 r5
ldr r5, [r1, #1*4]
add r8, r5
str r8, [r0, #0*4]
/*=== W[ 3] ===*/
ldr r14, T00_ADDR
ldr r9, T01_ADDR
ldr r8, T08_ADDR
ldr r7, T10_ADDR
ldr r6, T13_ADDR
add r2, r9, r11
/*(-- should do +0, +13, +8, -2tr --)*/
add r5, r14, r10
add r5, r8
sub r5, r2
S32_3 r9 r5
ldr r5, [r1, #4*4]
add r9, r5
str r9, [r0, #3*4]
/*=== W[ 6] ===*/
ldr r12, T00_ADDR
ldr r11, T03_ADDR
ldr r9, T04_ADDR
ldr r8, T11_ADDR
ldr r7, T13_ADDR
/*(-- should do +13, +4, -0, -11, -3 --)*/
add r5, r10, r9
sub r5, r14
sub r5, r8
sub r5, r11
S32_1 r8 r5
ldr r5, [r1, #7*4]
add r8, r5
str r8, [r0, #6*4]
/*=== W[ 9] ===*/
ldr r10, T00_ADDR
ldr r9, T03_ADDR
ldr r8, T06_ADDR
sub r4, r8, r11
/*(-- should do +0, +0tr, +1tr --)*/
add r5, r14, r4
add r5, r3
S32_4 r5
ldr r11, [r1, #10*4]
add r5, r11
str r5, [r0, #9*4]
/*=== W[12] ===*/
ldr r11, T09_ADDR
/*(-- should do +2tr, -0tr, -9 --)*/
sub r5, r2, r4
sub r5, r11
S32_2 r7 r5
ldr r5, [r1, #13*4]
add r7, r5
str r7, [r0, #12*4]
/*=== W[15] ===*/
ldr r14, T04_ADDR
ldr r12, T06_ADDR
ldr r10, T09_ADDR
ldr r9, T12_ADDR
ldr r7, T13_ADDR
sub r4, r9, r11
sub r3, r7, r12
/*(-- should do +0tr, +1tr, -4 --)*/
add r5, r4, r3
sub r5, r14
S32_0 r7 r5
ldr r5, [r1, #0*4]
add r7, r5
str r7, [r0, #15*4]
/*=== W[ 2] ===*/
ldr r14, T00_ADDR
ldr r7, T07_ADDR
ldr r6, T15_ADDR
/*(-- should do +0, +15, +7, -0tr --)*/
add r5, r14, r6
add r5, r7
sub r5, r4
S32_2 r7 r5
ldr r5, [r1, #3*4]
add r7, r5
str r7, [r0, #2*4]
/*=== W[ 5] ===*/
ldr r14, T02_ADDR
ldr r12, T03_ADDR
ldr r11, T10_ADDR
ldr r8, T12_ADDR
ldr r7, T15_ADDR
sub r4, r7, r14
sub r2, r12, r9
/*(-- should do +0tr, +10, +2tr --)*/
add r5, r4, r11
add r5, r2
S32_0 r12 r5
ldr r5, [r1, #6*4]
add r12, r5
str r12, [r0, #5*4]
/*=== W[ 8] ===*/
ldr r12, T05_ADDR
/*(-- should do +1tr, -0tr, -5 --)*/
sub r5, r3, r4
sub r5, r12
S32_3 r11 r5
ldr r5, [r1, #9*4]
add r11, r5
str r11, [r0, #8*4]
/*=== W[11] ===*/
ldr r11, T00_ADDR
ldr r9, T02_ADDR
ldr r8, T05_ADDR
ldr r7, T08_ADDR
ldr r6, T09_ADDR
sub r4, r7, r12
/*(-- should do +0tr, +9, -0, -2 --)*/
add r5, r4, r10
sub r5, r11
sub r5, r14
S32_1 r11 r5
ldr r5, [r1, #12*4]
add r11, r5
str r11, [r0, #11*4]
/*=== W[14] ===*/
ldr r11, T11_ADDR
/*(-- should do +0tr, +2tr, -11 --)*/
add r5, r4, r2
sub r5, r11
S32_4 r5
ldr r7, [r1, #15*4]
add r5, r7
str r5, [r0, #14*4]
/*=== W[ 1] ===*/
ldr r14, T06_ADDR
ldr r12, T08_ADDR
ldr r10, T11_ADDR
ldr r8, T14_ADDR
ldr r7, T15_ADDR
add r4, r11, r8
add r3, r12, r7
/*(-- should do +0tr, +6, -1tr --)*/
add r5, r4, r14
sub r5, r3
S32_1 r14 r5
ldr r5, [r1, #2*4]
add r14, r5
str r14, [r0, #1*4]
/*=== W[ 4] ===*/
ldr r14, T01_ADDR
ldr r12, T02_ADDR
ldr r7, T09_ADDR
/*(-- should do +1, +2, +9, -0tr --)*/
add r5, r14, r12
add r5, r7
sub r5, r4
S32_4 r5
ldr r8, [r1, #5*4]
add r5, r8
str r5, [r0, #4*4]
/*=== W[ 7] ===*/
ldr r12, T01_ADDR
ldr r11, T04_ADDR
ldr r8, T05_ADDR
ldr r7, T12_ADDR
ldr r6, T14_ADDR
/*(-- should do +1, -12, -14, -4, -5 --)*/
sub r5, r14, r7
sub r5, r6
sub r5, r11
sub r5, r8
S32_2 r14 r5
ldr r5, [r1, #8*4]
add r14, r5
str r14, [r0, #7*4]
/*=== W[10] ===*/
ldr r14, T01_ADDR
ldr r8, T04_ADDR
ldr r7, T07_ADDR
add r4, r11, r7
/*(-- should do +1tr, -0tr, -1 --)*/
sub r5, r3, r4
sub r5, r14
S32_0 r14 r5
ldr r5, [r1, #11*4]
add r14, r5
str r14, [r0, #10*4]
/*=== W[13] ===*/
ldr r14, T02_ADDR
ldr r12, T10_ADDR
ldr r11, T11_ADDR
/*(-- should do +0tr, +10, +11, +2 --)*/
add r5, r4, r12
add r5, r11
add r5, r14
S32_3 r14 r5
ldr r5, [r1, #14*4]
add r14, r5
str r14, [r0, #13*4]
sub SP, #16*4
/*=== W[ 0] ===*/
ldr r14, [r1, #5*4]
ldr r3, [r2, #5*4]
eor r14, r3
str r14, [SP, #5*4]
ldr r12, [r1, #7*4]
ldr r3, [r2, #7*4]
eor r12, r3
str r12, [SP, #7*4]
ldr r11, [r1, #10*4]
ldr r3, [r2, #10*4]
eor r11, r3
str r11, [SP, #10*4]
ldr r10, [r1, #13*4]
ldr r3, [r2, #13*4]
eor r10, r3
str r10, [SP, #13*4]
ldr r9, [r1, #14*4]
ldr r3, [r2, #14*4]
eor r9, r3
str r9, [SP, #14*4]
sub r8, r9, r12
/*(-- should do +10, +13, +1tr, +5 --)*/
add r3, r11, r10
add r3, r8
add r3, r14
S32_0 r7 r3
ldr r3, [r1, #1*4]
add r7, r3
str r7, [r0, #0*4]
/*=== W[ 3] ===*/
ldr r7, [r1, #0*4]
ldr r3, [r2, #0*4]
eor r7, r3
str r7, [SP, #0*4]
ldr r6, [r1, #1*4]
ldr r3, [r2, #1*4]
eor r6, r3
str r6, [SP, #1*4]
ldr r5, [r1, #8*4]
ldr r3, [r2, #8*4]
eor r5, r3
str r5, [SP, #8*4]
add r4, r6, r11
/*(-- should do +0, +13, +8, -2tr --)*/
add r3, r7, r10
add r3, r5
sub r3, r4
S32_3 r6 r3
ldr r3, [r1, #4*4]
add r6, r3
str r6, [r0, #3*4]
/*=== W[ 6] ===*/
ldr r9, [r1, #3*4]
ldr r3, [r2, #3*4]
eor r9, r3
str r9, [SP, #3*4]
ldr r6, [r1, #4*4]
ldr r3, [r2, #4*4]
eor r6, r3
str r6, [SP, #4*4]
ldr r5, [r1, #11*4]
ldr r3, [r2, #11*4]
eor r5, r3
str r5, [SP, #11*4]
/*(-- should do +13, +4, -0, -11, -3 --)*/
add r3, r10, r6
sub r3, r7
sub r3, r5
sub r3, r9
S32_1 r5 r3
ldr r3, [r1, #7*4]
add r5, r3